In the field of frequency synthesis, there are three major technologies: analog direct frequency synthesis, digital direct synthesis (DDS) and indirect frequency synthesis based on phase-locked loop (PLL). For on-chip clock generation, PLL has been the designers' first choice due to its easy integration with other circuitries on chip. However, in most PLL designs, the implementation is in an analogy-digital mixed-signal style. In other words, large amount of analog circuits are required. This is mainly due to the oscillator (VCO) used in the design, which is an analog component.
In recent years, an all-digital phase-locked loop (ADPLL) becomes a popular member in phase-locked loop PLL family. The noticeable feature of ADPLL is a digital oscillator contained inside the ADPLL, which is capable of controlling by a digital value a frequency of a clock signal produced by the digital oscillator. Compared with a conventional phase-locked loop, the all-digital phase-locked loop (ADPLL) reduces analog design complexity, which makes it suitable for being implemented on digital processes. However, the “digital oscillator” in such ADPLL is not a digital circuit. It still comprises large amount of analog circuitries. It is termed digital oscillator simply for the reason that its frequency tuning is achieved through digital control.
Therefore, an all-digital phase-locked loop and an all-digital frequency-locked loop are required.